1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having hierarchically structured bit lines. Furthermore, the present invention relates to a system including the semiconductor device.
2. Description of Related Art
Some semiconductor devices such as DRAM (Dynamic Random Access Memory) include local bit lines and global bit lines that are hierarchically structured (see U.S. Pat. No. 5,682,343). The local bit line corresponds to a low-order bit and is connected to a memory cell. On the other hand, the global bit line corresponds to a high-order bit and is connected to a sense amplifier. With hierarchized bit lines, it is possible to increase the number of memory cells allocated to one sense amplifier, while shortening a line length of the local bit line that has a relatively high electrical resistance.
A semiconductor device described in U.S. Pat. No. 5,682,343, adopts a so-called open bit architecture. That is, a pair of global bit lines connected to a sense amplifier is allocated to different memory mats from each other. As is widely known, unlike a folded bit line architecture, because word line noise is not canceled in the open bit architecture, the word line noise is superimposed on a bit line of an access side. To deal with this problem, as shown in FIGS. 18 and 19 of U.S. Pat. No. 5,682,343, a dummy word line is used to cancel word line noise.
In case of the open bit architecture, a process for memory mats at both edges in a bit line direction becomes a problem. That is, in the open bit architecture, when a certain memory mat is selected, memory mats at both sides adjacent to the selected memory mat in the bit line direction are used as reference sides. However, for a memory mat that is located at an edge, only an adjacent memory mat exists in the bit line direction at one side. Therefore, although the memory mat located at the edge occupies the same dimension as a normal memory mat, its memory capacity becomes a half of a memory capacity of the normal memory mat.
To deal with this problem, for example, as shown in FIG. 3 of Japanese Patent Application Laid-open No. 2000-260885, a measure has been proposed in which a bit line is replicated for a memory mat that is located at an edge. The characteristic of two bit lines at an access side and a reference side to be input to a sense amplifier 3a that is sandwiched by a dummy memory cell array 2 and a normal memory cell array 1 is that a length a of a bit line included in the normal memory cell array 1 at the access side is equal to a length b of a bit line (a replicated line 11) included in the dummy memory cell array 2 at the reference side.
By replicating the bit line included in the dummy memory cell array 2 at the reference side (b=1/2a) in a cell array of the open bit line structure, a reduction of a dimension of a memory cell array arranged at the edge (an edge mat) is realized.
However, in a semiconductor device described in Japanese Patent Application Laid-open No. 2000-260885, the memory mat (the dummy memory cell array 2) that is located at the outermost edge has a configuration different from that of the other memory mat (the normal memory cell array 1), and the memory capacity (the number of memory cells) is a half of the number of memory cells of the other memory mat. In other words, attention needs to be paid to a fact that the number of memory cells to be connected to a bit line of an access side (four) and the number of memory cells to be connected to a bit line of a reference side (four), in which these memory cells are all connected to one sense amplifier 3a, are equal to each other. Therefore, an address allocation and the like are different from those of the other memory mat, leading to a complicated design. Furthermore, in the semiconductor device described in Japanese Patent Application Laid-open No. 2000-260885, because bit lines are not hierarchized, a layout to be taken is not clear if a hierarchized bit line structure is adopted. Specifically, when the memory capacity of the normal memory cell array 1 (the number of cells=a) increases, the memory capacity of the dummy memory cell array 2 (the number of cells=b) also increases, followed by an increase of the length b of the corresponding dummy bit line. That is, even if the hierarchized bit line structure is combined with the semiconductor device described in this conventional technique, the size of the dummy memory cell array 2 depends on the memory capacity of the normal memory cell array 1.